1. Field of the Invention
The present invention relates generally to a method for fabricating tungsten local interconnections in high density CMOS circuits, and also to high density CMOS circuits having local interconnections formed of tungsten.
More particularly, the subject invention pertains to a method for forming tungsten local interconnections in CMOS technology using reactive ion etching, and also to the high density CMOS circuits formed pursuant thereto. Borderless contacts are formed with the aid of a chromium etch stop layer beneath the tungsten local interconnection layer. This approach allows partial overlap of contacts to reduce device dimensions, and results in improved density and performance.
2. Discussion of the Prior Art
Recent increases in packing densities for complementary metal oxide semiconductor (CMOS) transistor circuits can be directly attributed to a reduction in device dimensions. For these trends to continue, interconnections between devices may require alternatives to conventional metallization techniques to keep pace with the smaller feature sizes. One alternative method is the use of local interconnections (LI) which may be used to wire circuit elements over limited distances.
Much of the previous work using local interconnections has focused on materials such as TiSi.sub.2, TiN, and TiW or CoSi.sub.2 which all rely on selective methods to pattern the local interconnections. While it is advantageous from a density standpoint to form self-aligned contacts with such approaches, there is much concern regarding their manufacturability, which does not appear to be feasible at the present time.
Non-selective methods have not received much attention in the prior art because of the difficulty in patterning metals over topography. However, it should be noted that one study reported the use of tungsten (W) local interconnections in 64K SRAM's without revealing the process details of their formation, P. A. Hunt, Appl. Surf. Sci., 38, 485 (1989).
The difficulty in patterning metal layers using reactive ion etching (RIE) results from the inability to avoid removing (or damaging) underlying materials and circuits. For partially covered contacts, a silicided diffusion may be exposed on one portion of the wafer, while oxide isolation is exposed in another region thereof.